The present invention relates generally to phase locked loop circuits, and in particular, to a circuit for calibrating an LCPLL.
On-chip transmitters and receivers typically use PLLs (phase locked loops) to generate accurate clocks for transmitting and receiving data. With ever increasing data transfer rates, PLLs capable of generating accurate, high frequency clocks, e.g., in the ones or even tens of Giga Hertz magnitudes may be needed. LCPLLs (inductor capacitor PLLs), which may use inductor capacitor voltage controlled oscillators (LCVCOs), capacitive controlled tank oscillators, or other oscillators, may be used to deliver such high frequency clocks. Unfortunately, an oscillator (e.g., VCO) in an LCPLL typically has a limited tuning range. To address this, LCPLLs have used automatic frequency control (AFC) techniques to calibrate oscillator settings to conform about an operable control voltage range.
FIG. 1 shows a portion of an LCPLL with a conventional AFC implementation. The PLL loop portion includes a phase frequency detector (PFD), a charge pump (CP), and a low-pass filter (LPF), represented in block 106, and an LCVCO 108 (feedback path not shown for brevity). The PLL operates to generate an output clock (VCO Clk) that accurately tracks an input reference clock (Ref_Clk) using negative feedback to adjust the LCVCO based on a measured difference (or error) between the Ref_Clk and Fb_Clk, a signal fed back from the VCO Clk output. (For convenience, the path from VCO Clk to Fb_Clk is not shown, but VCO Clk is coupled back to Fb_Clk, either directly or indirectly via one or more other circuit blocks.)
The AFC portion includes frequency detector 102, calibration logic 104, and calibration voltage (Vmid) 110, coupled as shown. It typically runs once at power-up to calibrate the VCO frequency to be close to the target reference clock frequency. Initially, in the calibration mode, the “Cal” pathway switch is closed to apply a fixed voltage (Vmid) as the control voltage (Vctl) to the LCVCO. The LCVCO 108 includes a bank of capacitors that may be engaged or disengaged in different combinations, as set by the digital CapSel[N:0]input. This provides a range of adjustable capacitance values that correspond to an output frequency range. During calibration, the calibration logic 104 functions, based on the fixed Vmid control voltage, to adjust the capacitor value, as set by CapSel[N:0], so that the VCO Clk center frequency is sufficiently close to a target operating frequency (as set by Ref13Clk). Vmid, as implied by its name, is typically set to be in the middle of the operating control voltage (Vctl) range so that a sufficient degree of adjustability is available during PLL operation.
After AFC completes, the PLL is allowed to lock normally. Unfortunately, the VCO may have an undesirable temperature coefficient, which causes the VCO frequency to change with temperature for a fixed control voltage value. Due to this, the PLL control voltage (Vctl) during lock will change as temperature changes. For a large enough temperature change, if the VCO temperature coefficient is large, the control voltage can become too low or too high for the PLL to stay locked. Even if the change isn't large enough to cause the PLL to lose lock, the control voltage change may still cause the PLL bandwidth or jitter to fall out of spec as the temperature changes.
Accordingly, new solutions may be desired.